The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 1998

Filed:

Jun. 07, 1996
Applicant:
Inventor:

Kenneth Rush, Colorado Springs, CO (US);

Assignee:

Hewlett-Packard Company, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257723 ; 257776 ; 257784 ; 257692 ; 257725 ; 257208 ; 257203 ; 257698 ;
Abstract

A multi-chip module including a multi-layer substrate and a patterned metallization layer formed on each layer of the substrate. A multi-tiered cavity is formed with an integrated circuit (IC) mounting surface at the bottom of the multi-tiered cavity. A plurality of ICs are mounted on the IC mounting surface of the cavity. A first set of wire bonds extends from at least one IC to the exposed portions of patterned metallization of at least two tiers of the multi-tiered cavity. A second set of wire bonds extends from the at least one IC to bond pads of an adjacent IC. A third set of wire bonds extends from the at least one IC to bond pads of the adjacent IC such that the third set of wire bonds has a higher loop height than the second set of wire bonds.


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