The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 1998

Filed:

Sep. 30, 1994
Applicant:
Inventors:

Junichi Shishizuka, Tokyo, JP;

Yoshinobu Mita, Kawasaki, JP;

Yoshihiro Ishida, Kawasaki, JP;

Miyuki Enokida, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395511 ; 395405 ; 395508 ;
Abstract

In a memory-to-memory data transfer apparatus, each of a plurality of memories connected to a memory bus is sequentially selected, and data which occupy predetermined positions in the data read from the selected memory are combined into a set of data. The set of data is sequentially written while addresses in the remaining memory is being updated. Alternatively, a plurality of sets of data are sequentially read out while addresses in a memory are being updated, and data which occupy predetermined positions in the read data are combined into a set of data. The set of data is written while the remaining memories are being sequentially selected. The apparatus may have a plurality of memories connected to a data bus and address generators for generating unique addresses for each of the memories in accordance with a predetermined synchronizing signal. The apparatus, in preferred form, effects transfer of data in thinned-out form or phase-divided form by shifting a generated address or by adding a predetermined value to the address.


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