Rapid register file access by limiting access to a selectable register

Abstract

A register window file method and apparatus is disclosed. A register file is formed from a plurality of registers. The registers are grouped into a plurality of logical windows. Window selection logic selects among the logical windows and thereby limits access at any given time to the selected logical window. Because access is limited to only one window at a time, an individual register can be selected by specifying its virtual register number. Therefore, there is no need to translate from virtual address numbers to physical address numbers when accessing registers. This means that virtual register number to physical register number translation logic of the prior art is no longer required. Thus, the area on the integrated circuit chip formerly occupied by the translation logic is no longer required. Furthermore, the translation delays per instruction introduced by the translation logic are also eliminated. Moreover, each register only shares read and write lines with the other registers of its window. Therefore, the capacitive load associated with each bit line of the register file is significantly smaller than that of the prior art where each register shared bit lines with every other register of the register file. Because selection is made only among the registers of a single window, smaller, less powerful drivers and sense amplifiers are required to write and read data respectively to and from the register file.