The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 1998
Filed:
Oct. 15, 1996
Dan Kikinis, Saratoga, CA (US);
Pascal Dornier, Sunnyvale, CA (US);
William J Seiler, Scotts Valley, CA (US);
Elonex I.P. Holdings, Ltd., London, GB;
Abstract
A personal digital assistant module with a local CPU, memory, and I/O interface has a host interface comprising a bus connected to the local CPU and a connector at a surface of the personal digital assistant for interfacing to a bus connector of a host general-purpose computer, providing direct bus communication between the personal digital assistant and the host general-purpose computer. In an embodiment, the personal digital assistant also stores a security code. The personal digital assistant according to the invention forms a host/satellite combination with a host computer having a docking bay, wherein upon docking a docking protocol controls access by the host to memory of the personal digital assistant based on one or more passwords provided by a user to the host. In another embodiment the personal digital assistant also has an expansion port connected to the local CPU, and expansion peripheral devices may be connected and operated through the expansion port. In another embodiment the local CPU has temperature sensing circuitry incorporated in at least one portion of the IC comprising the CPU, clock adjustment circuitry connected to the at least one portion, and control circuitry connected to the temperature sensor and to the clock adjustment circuitry, the control circuitry configured for driving the clock adjustment circuitry to provide an operational clock rate as a function of a temperature indication provided by the temperature sensor.