The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 1998
Filed:
Jan. 23, 1996
Vit F Novak, Los Altos, CA (US);
Sun Microsystems, Inc., Palo Alto, CA (US);
Abstract
Cold termination is provided at the bus output port of a last device coupled to a bus. Each device includes a termination integrated circuit ('TIC') that receives operating voltage from bus-provided V.sub.TERM potential. The TIC includes a series-coupled resistor-capacitor ('R-C') connected between V.sub.TERM and ground. The 'R-C' junction defines a SENSE node that is coupled to a groundable pin on the device bus output port and to a SENSE input node on the TIC. If a bus cable connector is attached to the device bus output port, attachment grounds the groundable pin, and thus the TIC SENSE node is '0', which disables TLC bus termination. But if no connector is attached, the groundable pin floats to a potential approximating V.sub.TERM, and is a logical '1', which enables TIC bus termination. Preferably an inverter is series-coupled between the TIC SENSE node and input SENSE node to accommodate a TIC that enables termination with a '0' input SENSE signal. A visual indicator coupled between V.sub.TERM and the inverter output illuminates when TIC bus termination is enabled. The present invention can cold terminate a wide-bus at a device, permitting the bus to propagate downstream as a narrow bus, and then cold terminate the narrow bus at the bus output port of a last device coupled to the bus.