The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 1998
Filed:
Mar. 02, 1995
Ranbir Singh, Macungie, PA (US);
Morgan Jones Thoma, Orlando, FL (US);
Lucent Technologies Inc., Murray Hill, NJ (US);
Abstract
An apparatus and method for providing improved latch-up immunity in a semiconductor device such as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. An exemplary apparatus includes a first region of semiconductor material of a first conductivity type, a well of semiconductor material formed in the first region and having a second conductivity type opposite to the first conductivity type, a first MOS transistor formed in the well and including a source region and a drain region formed of semiconductor material of the first conductivity type, and a second MOS transistor formed in the first region and having a source region and a drain region formed of semiconductor material of the second conductivity type. A conductive material or other suitable routing means is connected between the source region of one of the first or second MOS transistors and a corresponding voltage supply input of the device. In one embodiment, the routing means is formed of a semiconductor material having the same conductivity type as the source region, and may be a P.sup.+ or N.sup.+ active region. The source region of the first and/or second MOS transistor may be formed from a portion of the routing means.