Semiconductor memory including bit line reset circuitry and a pulse

Abstract

A semiconductor memory includes a power down pulse generating circuit having an output delay time which is dependent on the type of change or transition in an input signal. The pulse generating circuit generates a power down signal at different times depending on whether the input signal changes from a first level to a second level or from the second level to the first level to prevent the power down signal from being output twice when an input clock signal has a pulse width shorter than a normal pulse width thereof. The power down pulse generating circuit generates the power down signal in response to a signal from address transition detection circuitry, and causes data read/write circuitry and bit line pulse generating circuitry to become inactive to reduce power consumption. The bit line pulse generating circuitry generates reset signals which may be used to reset or precharge the bit lines at different timings to reduce peak current in the semiconductor memory.