The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 17, 1998
Filed:
Sep. 16, 1994
Randy Douglas Jester, Greer, SC (US);
Edwin Charles Culbertson, Rock Hill, SC (US);
Detlef M Frank, Mainz, DE;
Sherman Hall Rounsville, Greenville, SC (US);
John Arthur Penoyer, Greenville, SC (US);
Takeichi Tsugaka, Kurashiki, JP;
Minoru Onodera, Kurashiki, JP;
Toshiaki Sato, Kurashiki, JP;
Toru Sanefuji, Kurashiki, JP;
Hoechst Celanese Corp., Somerville, NJ (US);
Kuraray Company Ltd., Osaka, JP;
Abstract
The invention provides a multilayer microelectronic circuit board including a laminate of a plurality of circuit layers containing conductive vias within the layers or a combination of conductive vias and conductive wiring patterns on a surface of the layers, the layers comprising a first liquid crystal polymer and, interposed between said circuit layers, a layer of second liquid crystal polymer having a melting point of at least about 10.degree. C. lower than the melting point of the first liquid crystal polymer. The boards are produced by stacking a plurality of circuit layer sheets in appropriate electrical alignment such that they are separated by an interposed layer of the second liquid crystal polymer of lower melting point, and heating the stacked polymer sheets under pressure sufficient to bond the sheets or layers into a microelectronic printed circuit board, the temperature of the heating being sufficient to melt the lower melting second polymer but insufficient to melt the polymer present in the circuit layers. The second polymer layer may be interposed as a separate sheet during assembly or may be present as one or two separate surface layers in contact with the higher melting point polymer of the circuit layers.