The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 1998

Filed:

May. 26, 1995
Applicant:
Inventors:

Mario D Nemirovsky, San Jose, CA (US);

Robert James Divivier, San Jose, CA (US);

Robert Walter Williams, San Jose, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
395568 ; 3642755 ; 39518306 ; 39518504 ; 395704 ;
Abstract

A computer with a pipelined processor and code breakpoints for performing software debug operations includes prefetch and decode stages, debug address registers for storing code breakpoints representing addresses of preselected instructions, and two digital comparators. During the instruction prefetch phase of operation, the first comparator compares the 29 most significant bits �31:3! of the 32-bit prefetch instruction address against the code breakpoints stored in the debug address registers and produces a 1-bit signal indicating whether such comparison results in a positive match. Subsequently, during the decode phase of operation, the second comparator compares the three least significant bits �2:0! of the 32-bit prefetch instruction address and produces a 1-bit signal indicating whether such comparison results in a positive match. These two 1-bit signals are then logically ANDed, synchronized with bit 3 �2! of the 32-bit prefetch instruction address to ensure that such two 1-bit signals are based upon corresponding comparisons of the same prefetch instruction address.


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