Method and apparatus for reducing write cycle wait states in a non-zero

Abstract

A method and apparatus which enhances computer system performance in systems that incorporate a cache system that requires a first non-zero number of wait states and a memory system write buffer that requires a second lesser number of wait states. The present invention reduces or eliminates wait states that are otherwise required during write cycles in prior art designs without adding cost. During burst writes to data entries cached in the second level cache system, a cache protocol is used whereby the cache controller snoops the respective addresses which are the target of the burst write cycle out of the cache system, i.e., marks the respective cache line invalid. This effectively eliminates the data from the cache at the beginning of the burst write cycle. Since the data has now been marked invalid, the cache line is not required to be updated. Thus, the second level cache system effectively behaves as a write through cache system on these bursted writes, and the bursted writes pass through the cache system directly to the zero wait state write buffer in the memory controller. Therefore, the present invention increases system performance by reducing the write latency and thus improves the overall memory bandwidth of the processor.