The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 1998

Filed:

Mar. 01, 1995
Applicant:
Inventors:

Makoto Ichida, Yokohama, JP;

Kazutaka Nogami, Tokyo, JP;

Shigeru Tanaka, Fujisawa, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kanagawa-ken, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395449 ; 395470 ; 395471 ; 395463 ; 395455 ; 395440 ;
Abstract

A method for processing data by utilizing hierarchial cache memories in a system where a lower cache is connected between a processor and a higher cache memory and the higher cache memory is in turn connected to a main memory or connected through a serial arrangement of higher cache memories to the main memory. When a cache miss occurs in the lower cache and the lower cache is full of 'dirty data', the data is not written to the main memory but instead to the higher cache. Dirty data is written into the main memory when at least all of the cache memories are filled with dirty data and a cache miss occurs.


Find Patent Forward Citations

Ichida, Makoto. (1998). Method for processing data by utilizing hierarchical cache memories and (U.S. Patent No. 5717890). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5717890

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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