The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 1998

Filed:

Jul. 05, 1996
Applicant:
Inventor:

William Shields Neely, Campbell, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395 24 ; 364488 ;
Abstract

A system and method for designing a fixed weight analog neural network to perform analog signal processing allows the neural network to be designed with off-line training and implemented with low precision components. A global system error is iteratively computed in accordance with initialized neural functions and weights corresponding to a desired analog neural network configuration for analog signal processing. The neural weights are selectively modified during training and then expected values of weight implementation errors are added thereto. The error adjusted neural weights are used to recompute the global system error and the result thereof is compared to a desired global system error. These steps are repeated as long as the recomputed global system error is greater than the desired global system error. Following that, MOSFET parameters representing MOSFET channel widths and lengths are computed which correspond to the neural functions and weights. Such MOSFET device parameters are then used to implement the desired analog neural network configuration.


Find Patent Forward Citations

Loading…