The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 1998
Filed:
Nov. 28, 1994
Applicant:
Inventors:
Marco Maccarrone, Palestro, IT;
Marco Olivo, Bergamo, IT;
Assignee:
SGS-Thomson Microelectronics S.r.l., Agrate Brianza, IT;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R / ;
U.S. Cl.
CPC ...
371 222 ; 371 225 ;
Abstract
A circuit architecture for testing a programmable logic matrix, e.g., the PLA type, has a group of input latches and a corresponding group of output latches connected to the matrix, and test information paths structured with at least one data bus and one address bus. The input latch and the output latch are connected electrically to the test data bus and to the test address bus to allow matrix testing with considerable time saving over known circuitry.
Maccarrone, Marco. (1998). Method and apparatus for testing a network with a programmable logic (U.S. Patent No. 5717698). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5717698
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