The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 1998

Filed:

Jun. 05, 1995
Applicant:
Inventors:

Kiyofumi Kawamoto, Hyogo, JP;

Shinichi Nakagawa, Hyogo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F / ;
U.S. Cl.
CPC ...
364784 ;
Abstract

A selecting circuit is formed of two tristate gates. The size of each of a plurality of transistors configuring a tristate gate processing a signal having a shorter delay time is set smaller than the size of each of a plurality of transistors configuring a tristate gate processing a signal having a longer delay time, so that the capacitance of the former transistors is decreased. As a result, the load to be driven by each of transistors to which a signal having a longer delay time is applied is decreased, whereby the entire circuit can be increased in operation speed. Accordingly, the selecting circuit selecting between two or more input signals having different delay times can operate at a high speed.


Find Patent Forward Citations

Kawamoto, Kiyofumi. (1998). Selecting circuit including circuits having different time constants to (U.S. Patent No. 5717622). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5717622

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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