The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 1998
Filed:
Jun. 24, 1996
Akio Ishizuka, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A method for designing an interconnection route in an LSI includes steps of finding a minimum-cost path among possible paths for a current net, the possible paths overlapping with existing nets routed before the current net. A unit cost assigned to a grid for scoring possible paths includes a length cost and a rip-up and reroute cost for ripping-up and rerouting the existing nets overlapping with the current net in the grid. The rip-up and reroute cost is not scored, however, when the existing nets also overlaps with the current net in another grid so far routed. The route will be possibly selected in a path overlapping with a several wire segments of a single existing net rather than overlapping with a single segment of each of a plurality of existing nets. Number of rip-up and reroute procedure is reduced so that the speed of routing process is improved, providing a lower cost for routing an interconnection route in a computer.