Cyclic redundancy check synchronizer

Abstract

A cyclic redundancy check synchronizer includes an N-byte shift register for shifting an input byte string by N bytes and N-1 bytes, a compensation polynomial driver for driving a compensation polynomial by modulo-2-dividing bits of a byte output from the Nth stage of the N-byte shift register by a generator polynomial and shifting the resultant remainder by one bit in a direction toward higher-order bits, and a calculator for inputting bits of an output byte from a remainder register as high-order bits and bits of an input data byte as low-order bits and for performing compensation polynomial modulo-2 subtraction and generator polynomial modulo-2 division for the inputted bits. The cyclic redundancy check synchronizer also includes a block synchronization identifier for searching for syndrome output signals from the calculator at an interval of a byte time to check whether the same syndrome signal is outputted from the calculator successively a predetermined number of times or more at an interval of a block period, and a data selector for selecting bits constituting a byte from among output bits from the N-byte shift register according to a certain one of the syndrome output signals from the calculator resulting in a block synchronous state in response to a data selection signal from the block synchronization identifier to output byte-synchronized data.