Semiconductor memory device with stacked capacitor structure

Abstract

In a semiconductor memory device with a stacked capacitor structure, a MOS transistor is formed on a substrate to have a gate electrode, a source region and a drain region. An insulating film is formed on the MOS transistor with an opening passing through the insulting film to one of the source and drain regions of the MOS transistor. A conductive storage electrode is formed such that it is connected to the one of the source and drain regions of the MOS transistor and has a first portion extending along a top surface of the insulating film and a second portion provided at each of edges of the first portion, and including a first subportion extending in an upper direction from an upper surface of the first portion and a second subportion below a lower surface of the first portion. Then, a capacitive insulating film is deposited and a conductive plate electrode film is deposited on the capacitive insulating film to complete a memory cell capacitor with the conductive storage electrode, the capacitive insulating film and the conductive plate electrode. The conductive storage electrode is formed by depositing a first conductive film on the insulating film and forming the first portion of the conductive storage electrode from the first conductive film, etching a surface portion of the insulating film where the first portion is not formed, and depositing a second conductive film and forming the storage electrode second portion from the second conductive film.