The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 1998
Filed:
Feb. 16, 1996
Hajime Sato, Yokohama, JP;
Shuichiro Ishizawa, Kamakura, JP;
Nozomu Harada, Yokohama, JP;
Kiyofumi Ochii, Koganei, JP;
Shigeyuki Hayakawa, Chigasaki, JP;
Yoshiro Aoki, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A liquid crystal display device of low power consumption is disclosed, which is suitable for use with a portable data processing apparatus, in particular. The liquid crystal display device, comprises: a switch element array substrate (301) having a plurality of data lines (1) and a plurality of scanning lines (2) both arranged being intersected to each other in a matrix form so as to form matrix intersection points; a plurality of pixel electrodes (3) each arranged for each matrix intersection point; and a plurality of first switching elements (6, 7) each arranged for each matrix intersection point and each turned on or off by the scanning line, for applying write voltage supplied from the data line to the pixel electrode, respectively when turned on; a counter substrate (314) having a plurality of counter electrodes (12) each arranged being opposed to each pixel electrode with a gap between the two; a liquid crystal layer (13) sandwiched between the switching element array substrate and the counter substrate; a plurality of memory elements (100) each interposed between the corresponding first switching element and the corresponding pixel electrode, for holding the write voltage supplied through the data line as data, when the first switching element is turned on; a plurality of display control lines (8, 10) each arranged in correspondence to each scanning line; and a plurality of second switching elements (9, 11) each arranged for each matrix intersection point, for controlling connection between the pixel electrode and the display control line on the basis of output of the memory element.