Fuse element for a semiconductor memory device

Abstract

An electrically programmable fuse element includes a fuse having a first end coupled to a data output node selectively coupled, e.g., via a PMOS pull-up transistor, to a power source voltage, e.g., Vcc or Vpp, and a second end, a bipolar transistor connected between the second end of the fuse and a reference potential (e.g., Vss), a first MOS transistor having a channel connected between the base of the bipolar transistor and the reference potential, and a gate electrode coupled to a fuse program control signal, a second MOS transistor having a channel connected between the second end of the fuse and the reference potential, and a gate electrode coupled to a read-out control signal. In a fuse program mode of operation, the second MOS transistor is turned off, and the first MOS transistor is turned on in response to the fuse program control signal, whereby a base current is caused to flow through the first MOS transistor and a fuse program current is caused to flow through the fuse, said first current being equal to the base current multiplied by an amplification ratio (e.g., 10 or greater) of the bipolar transistor and being sufficient to open said fuse. In a read-out mode of operation, the first MOS transistor and the bipolar transistor are turned off, and the second MOS transistor is turned on in response to the read-out control signal, whereby a second current is caused to flow through the fuse, the second current being less than the first current and insufficient to open the fuse.