Clock phase alignment using frequency comparison

Abstract

Systems and methods for phase aligning the clocks signal transmitted from a source to multiple destination devices over individual transmission lines of differing impedance. According to the invention, each clock signal transmission line has associated therewith a matching pair of transmission lines connected to oscillate as a dummy loop. Matching programmable delay lines are connected in series with the clock signal line and the dummy loop lines, the delay lines being commonly controlled in response to a frequency comparison between the oscillation on the dummy loop and a direct subharmonic of the clock frequency. When the oscillation frequency of the dummy loop and the subharmonic of the base clock frequency match, the clock signal at the destination chip is phase aligned to the base clock signal at the clock chip, though shifted by one clock period. Clock signal phase alignment is automated for each destination chip subject to individualized control and is thereby automatically responsive to thermal or other changes at the clock chip or individual destination chips.