The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 1998
Filed:
Nov. 09, 1995
Reinhold Kaiser, Heilbronn, DE;
Temic Telefunken microelectronic GmbH, Heilbronn, DE;
Abstract
A method for manufacturing integrated circuits complete with integrated low loss capacitances, inductances, and high Q resistors. Initially a large number of monocrystalline--in their lateral and vertical directions dielectrically insulated--boxes for receiving the active devices of the integrated circuit are generated on a semiconductor substrate wafer with high resistivity. A subset of the completely insulated boxes is to provide for receiving the active devices generated by appropriate bipolar, MOS, or BiCMOS technologies. The other subset is to provide for receiving the passive devices. From these boxes, the monocrystalline semiconductor material is removed completely. In the empty boxes, the walls of which boxes consist of a dielectric, thin film conductor structures are defined by deposition and lithographic processes, eventually forming the passive devices. Due to the layer combination of thin film conductor/dielectric/substrate with high resistivity, the passive devices manufactured in these boxes will be marked by very low losses only, i.e. they are possessed of a high quality (Q).