Parallel computer comprised of processor elements having a local memory

Abstract

A parallel computer includes a plurality of processor elements (1-1 to 1-n) connected by a network (2); each processor element includes a local memory (6) for holding a program and related data, a processor (3) for performing an instruction in said program, a circuit (5) for transferring data to other processor elements, and a circuit (4) for receiving data sent from another processor element; a memory area (92,8) includes of a plurality of reception data areas for temporarily storing data received by said receiving circuit, and memory (92,8) constructed of a plurality of tag areas, provided for each reception data area, for storing a data tag indicating validity of data in the corresponding reception data area; a transmitting circuit (5) for transmitting data with an attached data identifier predetermined by said data; a circuit for writing the data into one of the plurality of reception data areas in response to data received from the network, and writing valid data tag into one of said plurality of reception data areas, the receiving circuit being parallelly-operated with the processor; and, an access circuit (38) for reading both data and tag from one of the reception data areas determined by the data identifier and from the corresponding tag areas, in response to a data identifier designated by the instruction which is produced from said program for requiring data reception, and for repeatedly reading a tag and data from the tag reception data areas until a valid data tag is read therefrom.