Microprocessor having address pre-outputting function and data processor

Abstract

A microprocessor accesses a first and second area of an external memory by outputting common addresses excluding a least significant bit of the actual addresses. The first area stores even addresses and the second area stores odd addresses. The microprocessor comprises a microprocessor core generating the actual addresses, an address counter generating a pre-output address value obtained by, at a start of every accessing to the second area, sequentially incrementing from an initial value obtained by excluding the least significant bit from the actual address generated by the microprocessing core, an address latch latching the pre-output address value, a control circuit controlling the address latch to latch the pre-output address value and provide the pre-output address value to the memory after accessing the memory, and an address comparator. The address comparator, at the time of accessing the first and second areas, compares the value obtained by excluding the least significant bit from the actual address generated by the microprocessing core and the pre-output address value latched by the address latch, and outputs a hit signal upon coincidence. The control circuit controls the address counter and the address latch to latch the value obtained by excluding the least significant bit from the actual address when the address comparator does not output a hit signal. Thus, an access time can be shortened at reading a plurality of sequential data successively from the memory whose access time is relatively long.