The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 1998

Filed:

Apr. 28, 1995
Applicant:
Inventor:

Naresh Ramnath Shanbhag, Scotch Plains, NJ (US);

Assignee:

Lucent Technologies, Murray Hill, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L / ;
U.S. Cl.
CPC ...
375234 ; 370537 ;
Abstract

An initial phase-loading circuit (IPLC) for a fractionally-spaced linear equalizer (FSLE) includes a signal coupling component adapted to be coupled to the FSLE in a configuration so as to selectively introduce time-shifted discrete signals. The FSLE includes a set of initial filter tap coefficients that provide a discrete signal to the FSLE, perform discrete signal equalization using the FSLE at least until substantial convergence of the filter tap coefficients, and provide to the FSLE a time-shifted discrete signal to replace the previously provided discrete signal.


Find Patent Forward Citations

Shanbhag, Naresh. (1998). Initial phase-loading circuit for a fractionally-spaced linear equalizer (U.S. Patent No. 5710794). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5710794

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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