Pipeline analog to digital converter architecture with reduced mismatch

Abstract

A multistage pipelined analog to digital converter architecture that significantly reduces non-linearity by a novel control switching technique is introduced. A first aspect of the present invention embraces a sample and hold circuit that includes a logic circuit, a plurality of reference signal nodes, an input signal node, an output signal node, a sample signal node, a first switching node, a second switching node, a circuit reference node, a first capacitor, a second capacitor, a signal routing circuit, and amplifier, which are inter-coupled to provide an output analog residue signal. At each stage of the pipelined architecture the sample and hold switch control logic alternately samples and amplifies signals inputted thereto and effectively reduce capacitor mismatch errors. This has the advantageous result of reducing non-linearity. According to a second aspect, the sample and hold circuit uses a differential amplifier having an inverting input and a non-inverting input. This second aspect further employs sequential termination of the amplifying time period resulting in additional advantage of reducing charge injection.