The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 20, 1998
Filed:
Apr. 29, 1996
Shye Lin Wu, Hsinchu, TW;
Vanguard International Semiconductor Corporation, Hsin-Chu, TW;
Abstract
A method for forming a tungsten silicide polycide gate electrode within a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and the tungsten silicide polycide gate electrode which is formed through the method. Formed upon a semiconductor substrate is a gate oxide layer. Formed upon the gate oxide layer is a first polysilicon layer which is formed through annealing a first amorphous silicon layer. Formed upon the first polysilicon layer is a second polysilicon layer which is formed through annealing a second amorphous silicon layer. Formed upon the second polysilicon layer is a tungsten silicide layer formed through a Chemical Vapor Deposition (CVD) method. The first polysilicon layer and the second polysilicon layer have a crystallite size no greater than about 0.3 microns, and the first polysilicon layer and the second polysilicon layer have a dopant concentration larger than about 1E16 atoms per cubic centimeter. Optionally, at least a third polysilicon layer may be added through annealing at least a third amorphous silicon layer between the second polysilicon layer and the tungsten silicide layer. Optionally, an fourth amorphous silicon layer may be added directly beneath the tungsten silicide layer.