Circuit for detecting a synchronization byte of a transport stream

Abstract

A circuit for detecting a synchronization byte when a decoder of a MPEG 2 system performs a parsing on a transport stream. The circuit includes a shift register for receiving a transport packet, 1 byte at a time whenever a clock signal is received, and for outputting the packet to a first comparing device which compares a hexadecimal value 47 (OX47) and the value received from the shift register. A logical sum device sums the signal output from the first comparing device and a reset signal. A first counter has a value of 0 or 1 according to the value output from the first comparing device whenever a clock signal is input to the first counter. A second comparing device is provided for comparing the decimal value of 188 and the value of the first counter. A logical multiplication device multiplies the value output from the first comparing device with the value output from the second comparing device. The value of a second counter is increased by the output from the logical multiplication device when the output of both the first comparing device and the second comparing device is 1. Finally, the circuit includes a third comparing device which compares the value of the second counter and the decimal value 2, and a fourth comparing device which determines a value of a synchronization byte detecting flag by comparing the output of the first comparing means and the output of the third comparing means.