The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 1998
Filed:
Nov. 01, 1995
Norio Higashisaka, Itami, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
In a variable delay circuit including a high-speed clock generator receiving a trigger signal and outputting a pulse signal after a desired time interval upon rising of the trigger signal and a coarse delay signal generator, the high-speed clock generator includes a rising edge detector receiving the trigger signal, detecting a rising edge of the trigger signal, and outputting an edge detecting pulse having a time interval, and an asynchronous reset oscillator receiving the edge detecting pulse, being reset upon rising of the edge detecting pulse, and generating a high-speed clock upon falling of the edge detecting pulse. The high-speed clock generator of the variable delay circuit is realized without using analog circuits. Further, since the high-speed clock generator includes no PLL, it is not necessary to provide analog circuits, such as charge pump and VCO, in a digital LSI and, therefore, special considerations for the analog circuits are eliminated.