The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 1998
Filed:
Feb. 08, 1996
Applicant:
Inventor:
Yoshinori Inoue, Hyogo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
326 88 ; 326 26 ; 326 80 ; 326 82 ; 327390 ; 327589 ;
Abstract
When input signal IN rises to an 'H' level, node N1 attain an 'H' level, and output terminal OUT is charged to a level of VCC-V.sub.TH by n channel transistor. Capacitor is charged by the 'H' level signal transmitted through inverters, and the charged potential is superimposed on output terminal OUT. When a short pulse is merged with input signal IN, RS flipflop is latched, and node N1 attains an 'L' level, thereby discharging the voltage of the output terminal. When the output terminal attains an 'L' level, NAND gate is opened and RS flipflop is reset, thereby raising the output terminal again to a boost voltage.