The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 1998

Filed:

Sep. 10, 1996
Applicant:
Inventor:

Young-Soo Jang, Kyungki-do, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438294 ; 438304 ; 438305 ;
Abstract

Methods of forming field effect transistors having oxidation-controlled gate lengths include the steps of forming an insulated gate electrode on a face of semiconductor substrate. The gate electrode has exposed ends thereof which define an initial gate length. Source and drain region dopants are then implanted into first portions of the face, using the insulated gate electrode as an implant mask. The implanted first portions of the face and the exposed ends of the insulated gate electrode are then thermally oxidized to form a relatively thick oxide layer. During this step, the implanted dopants are diffused and bird's beak oxide extensions are formed at the upper and bottom corners of the gate electrode. The bird's beak oxide extensions are preferably formed to increase the separation distance between the gate electrode and the source and drain regions and thereby reduce the gate-source/drain capacitance and inhibit parasitic hot electron injection from the drain region. The step of thermally oxidizing the exposed ends of the insulated gate electrode also causes the ends to be consumed and the first portions of the face to become recessed. Thus, during oxidation, the length of the gate electrode can be reduced in a controlled manner and the degree of vertical overlap between the gate electrode and the diffused source and drain region dopants can be reduced to obtain a further reduction in the parasitic gate-source/drain capacitance. In addition, gate lengths having sub-micron dimensions can be achieved without requiring sub-micron photolithographic line widths to define the gate electrode.


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