The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 1997
Filed:
Jan. 30, 1992
Giulio Marotta, Rieti, IT;
Eros Pasero, Turin, IT;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A cell of MOS transistors for converting a voltage into a current for forming synapses of neural nets, in particular for converting the difference between an input voltage (V.sub.IN) and a voltage (V.sub.W) for weighting the synapse into a current, realized by means of a differential stage comprising a first transistor (M1) operating as a current generator, in which a first and a second branch in parallel end, which branches respectively comprise a second (M2) and a third (M3) push-pull connected transistor, to the gate regions of which the input voltage (V.sub.IN) and the voltage (V.sub.W) for weighting the synapse, and to which a fourth (M4) and a fifth (M5) transistor are respectively connected in series, in which the fourth (M4) and the fifth (M5) transistor are P-MOS transistors having their gate regions short-circuited and said fourth (M4) P-MOS transistor is connected as a diode, and in which the output current (I.sub.OUT) is drawn from the node (N) that connects said third (M3) and said fifth (M5) transistors inserted in series in said second branch of the circuit and a capacitor (c) is connected to the gate region of said third (M3) transistor to store the voltage (V.sub.W) for weighting the synapse applied to the circuit.