The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 23, 1997
Filed:
Nov. 06, 1995
R Loyd Harrison, Fullerton, CA (US);
Steven P Davies, Ontario, CA (US);
Hughes Aircraft Company, Los Angeles, CA (US);
Abstract
A modular array processor architecture (10) comprising a plurality of interconnected parallel processing node (11)s that each comprise a control processor (12), an arithmetic processor (13) having an input port (22) for receiving data from an external source that is to be processed, a node memory (14) that also comprises a portion of a distributed global memory, and a network interface (15) coupled between the control processor (12), the arithmetic processor (13), and the node memory (14). Data and control buses (17, 18) are coupled between the arithmetic processors (13) and network interfaces (14) of each of the processing nodes (11). Respective network interfaces (15) link each of the arithmetic processors (13), node memories (14) and control processors (12) together to provide for communication throughout the architecture (10) and permit each node to communicate with the node memories (14) of all other processing nodes (11). This linking, along with the use of a heuristic scheduling algorithm, provides for load balancing between the processing nodes (11). Data queues are segmented and distributed across the architecture (10) in a way that the source and destination nodes (11) process data locally in the memory (14), while overflow is kept in distributed bulk memories (14). The network interfaces (15) buffer data transferred over the data and control buses (17, 18) to a respective node (11). Also, the network interfaces (15) operate as high-speed DMA controllers to transfer data between the arithmetic processor (13) and node memory (14) of a processing node (11) independent of the operation of the control processor (12) in that node (11). The control bus (17) is used to keep track of available resources throughout the architecture (10) under control of a heuristic scheduling algorithm that reallocates tasks to available arithmetic processors (13) based on a set of heuristic rules to achieve the load balancing. The data bus (18) is used to transfer data between the node memories (14) so that reallocated tasks are performed by selected arithmetic and control processors (13, 12) using data that is stored locally.