Detecting segment limit violations for branch target when the branch

Abstract

A pipelined 32 bit x86 processor including a prefetch unit and a branch unit. During sequential prefetching, the prefetch unit increments a prefetch physical address PFPA and a corresponding prefetch linear address PFLA--for each prefetch address, the PFLA is compared with the code segment limit linear address CSLA to determine if the corresponding prefetch block of 16 instruction bytes (cache line) contains the segment limit. If a COF hits in the branch unit, it outputs corresponding target address information used to generate a prefetch address--this target address information includes bits �11:0! of the target address (which are the same for the target physical address), i.e., the branch unit does not provide a full PFLA for comparison with the CSLA. Instead, the prefetch unit compares the low order bits �11:0! of the target address supplied by the branch unit with the CSLA--if a partial match occurs indicating that the CSLA address is potentially within such target prefetch block, the prefetch unit asserts a segment limit violation state that inhibits any instruction bytes from the target prefetch block from being transferred to the decoder. When the full target linear address is generated during the address calculation stage, it is compared with the CSLA address--(i) if they do not match, the segment limit violation state is deasserted, or (ii) if they match, the segment limit violation state is adjusted such that the transfer of instruction bytes from the target prefetch block is permitted up to the segment limit as represented by the CSLA address, and then a segment limit violation is signaled.