The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 23, 1997
Filed:
Aug. 15, 1995
Gregory J Fisher, Indialantic, FL (US);
Chong I Chi, Palm Bay, FL (US);
Harris Corporation, Melbourne, FL (US);
Abstract
The invention is a circuit and method for selecting a plurality of different types of resisters and for reliably manufacturing a current generator across different wafer lots. In one embodiment, a monolithic current generator applies the output voltage of a voltage reference circuit across a plurality of series-connected resisters of different types. The resisters are preferably statistically independent resisters, which permits a total resistance with a predefined standard resistance deviation across manufacturing wafer lots. An output current may then be produced which has a predefined standard current deviation across manufacturing wafer lots. In a preferred embodiment, no more than six different types of resisters are used. The resisters may be chosen from the group consisting of diffused resisters, implanted resisters, thin film resisters, metal resisters, and composite resisters. The present invention also includes a method for reliably producing current generators across wafer lots. A plurality of voltage reference circuits are formed in electrical connection with a plurality of n different types of series-connected resisters in a plurality of semiconductor die. Preferably, the plurality of n statistically independent resisters are formed with each resistor of the plurality of statistically independent resisters having a predefined standard resistance deviation across manufacturing wafer lots. An output voltage from respective ones of the voltage reference circuits applied across respective ones of the plurality of n different types of resisters would produce a plurality of respective output currents. Each of the respective output currents preferably has a predefined standard current deviation across manufacturing wafer lots.