Cell architecture for mixed signal applications

Abstract

A cell architecture for mixed signal applications is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a transistor arrangement in which substrate taps are located adjacent to the transistor pairs. This provides for a more 'symmetric' cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity. The cell architecture includes a substrate tap area that allows for the accommodation of a plurality of electrically isolated metal lines.