The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 23, 1997
Filed:
Dec. 20, 1995
Hidetsuna Hashimoto, Kawasaki, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
According to the method of manufacturing a semiconductor device having a multilayer interconnection structure, lower wires are formed on a semiconductor substrate. Then, a first reflow SiO.sub.2 film having a reflow form is formed on the semiconductor substrate and the lower wires by reacting SiH.sub.4 gas with H.sub.2 O.sub.2 in a vacuum at 650 Pa or less within a range from -10 to 10.degree.C. After the first reflow SiO.sub.2 film is formed, heat treatment is performed at a predetermined high temperature on the semiconductor substrate on which the first reflow SiO.sub.2 film, and a second reflow SiO.sub.2 film having a reflow form is formed on the semiconductor substrate and the lower wires by reacting SiH.sub.4 gas with H.sub.2 O.sub.2 in a vacuum at 650 Pa or less within a range from -10 to 10.degree.C. The heat treatment step performed after the first reflow SiO.sub.2 film forming step and the second reflow SiO.sub.2 film forming step subsequent thereto are respectively performed at least once. After the abovementioned steps are finished, upper wires are formed on the second reflow SiO.sub.2 film.