The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 1997

Filed:

Jun. 07, 1995
Applicant:
Inventors:

George S Taylor, Menlo Park, CA (US);

P Michael Farmwald, Berkeley, CA (US);

Timothy P Layman, San Carlos, CA (US);

Huy Xuan Ngo, Santa Clara, CA (US);

Allen W Roberts, Union City, CA (US);

Assignee:

Silicon Graphics, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395471 ; 395449 ; 39542102 ;
Abstract

A method of invalidating a line in a designated cache in each level of a multiple level, multiple cache memory system. Each line of the cache memory system includes a tag field, a data field, and a bit indicative of the validity of the line. The method provides a software invalidate instruction which bypasses any address translation mechanism. Included in the software invalidate instruction is a first field to identify within which multiple cache the line is to be avoided. A target address is generated to index each level of the cache memory system. The state of the bit is changed in accordance with the address and the invalidate instruction.


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