The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 1997

Filed:

Mar. 28, 1996
Applicant:
Inventors:

Daniel P Gregerson, Half Moon Bay, CA (US);

David R Farrell, San Francisco, CA (US);

Sunil S Gaitonde, Daly City, CA (US);

Ratinder P Ahuja, Daly City, CA (US);

Krish Ramakrishnan, Union City, CA (US);

Muhammad Shafiq, El Granada, CA (US);

Ian F Wallis, Cupertino, CA (US);

Assignee:

Peerlogic, Inc., San Francisco, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L / ;
U.S. Cl.
CPC ...
370256 ; 370408 ; 3952001 ; 34082502 ;
Abstract

A method for independently executing software components in a node of a network containing many nodes. The method includes the step of generating a logical hierarchy of the roles of the nodes where any node can assume one or multiple roles, with the assumption of which neither requires nor precludes the assumption of any other role, and with the hierarchy having three or more levels. The method also includes the step of negotiating the role of the nodes when there is a change in the configuration of the network, with the node at the lowest level of the hierarchy being able to assume the role of the highest level of the hierarchy.


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