The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 1997
Filed:
Jul. 24, 1996
Applicant:
Inventors:
Tomohisa Wada, Hyogo, JP;
Motomu Ukita, Hyogo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ; G11C / ;
U.S. Cl.
CPC ...
365200 ; 365 63 ; 365 51 ;
Abstract
In a semiconductor memory cell array including word lines, bit lines, and a plurality of memory cells arranged at crossings between the word lines and the bit lines, the bit lines are grouped into odd and even numbered groups. A shift redundancy circuit is arranged between each group of odd or even bit lines and sense amplifier and write circuits for the purpose of shifting a defective memory cell to a redundant memory cell.
Wada, Tomohisa. (1997). Semiconductor memory device having two layers of bit lines arranged (U.S. Patent No. 5699308). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5699308
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile