The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 1997
Filed:
Jan. 11, 1996
Ray Farbarik, Seattle, WA (US);
William H Nicholls, Seattle, WA (US);
Cascade Design Automation Corporation, Bellevue, WA (US);
Abstract
A high-speed solid state buffer circuit and method for producing the same. A buffer circuit accepts logic input signals and transforms the signals to an output signal which can drive a heavy load. By using an output stage pull-up device that includes a parallel combination of an enhancement mode FET and a depletion mode FET, a solid-state buffer circuit with increased speed and output voltage swing is achieved. Most conveniently, the buffer takes the form of a logic inverter. However, the buffer can also be used to form a multiple input NOR gate. The circuit is most suitable for realization in GaAs technology.