The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 1997

Filed:

Jun. 20, 1996
Applicant:
Inventors:

Hiroshi Tomita, Yokohama, JP;

Mami Saito, Yokohama, JP;

Kikuo Yamabe, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257610 ; 257617 ; 257913 ; 437 10 ; 437 12 ;
Abstract

A semiconductor device includes a semiconductor substrate having first and second main surfaces and including a denuded zone, in which an oxygen concentration is lower than that in an inner portion of the semiconductor substrate and which does not include a bulk microdefect, and an intrinsic gettering zone, an element region formed on the first surface of the semiconductor substrate, and an extrinsic gettering layer, made of an amorphous semiconductor material which traps a metal impurity, and formed directly on at least a portion of the intrinsic gettering region or the denuded zone entirely or partially thinned of the second main surface of the semiconductor substrate. A method for manufacturing a semiconductor device includes the steps of forming an element region on a first main surface of a semiconductor substrate having first and second main surfaces and having an intrinsic gettering zone, and forming an extrinsic gettering layer, made of an amorphous semiconductor material which traps a metal impurity, directly on at least a portion of the intrinsic gettering region of the second main surface of the semiconductor substrate.


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