Flexible clock and reset signal generation and distribution system

Abstract

A flexible clock and reset signal generation and distribution system and method for distributing a relatively low frequency clock signal to various elements of a computer system that require higher frequency clock signals for operation and includes programmable frequency synthesizers containing phase locked loop (PLL) type frequency multipliers, which are located physically adjacent to the computer system elements for receiving the low frequency clock signal and generating the various required higher frequency clock signals. The source of the relatively low frequency clock signal is a real-time clock (RTC) module having a crystal oscillator, a reset signal generator, and a low voltage detector. The RTC module switches off the low frequency clock signal when the main system power supply falls below a prescribed voltage level, such as, a battery voltage, or a voltage reference, or a combination battery voltage and voltage reference. Further, the RTC module provides a system reset signal that is asserted a predetermined delay time after the low frequency clock signal is provided.