The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 1997
Filed:
Nov. 15, 1996
Ming-Liang Chen, Hsinchu, TW;
Chih-Hsun Chu, Hsinchu, TW;
Mosel Vitelic Inc., Hsinchu, TW;
Abstract
The present invention relates to a new process for fabricating integrated circuits, and more particularly, to a CMOS IC process method of low cost, shallow junction and no crystal defects. After the gate oxide and gate electrodes have been formed on the N-well and the P-well, an N.sup.- Lightly-Doped-Drain (N.sup.- LDD) is made, then the sidewall of the N-channel polysilicon gate and the P-channel polysilicon gate are covered with dielectric spacer. A layer of PhosphoSilicate Glass (PSG) is thereafter deposited and patterned on the N-well and the pickup area of the P-well by lithography and etching techniques. Ion implantation is used to build the P.sup.+ Source/Drain (S/D) electrode, after which the sidewall spacer of the P-channel polysilicon gate is removed and a blanket implantation of P dopant forms the P.sup.- LDD on the area of the N-well. The P-well is doped with N-type dopant with its source from PSG by high temperature diffusing and forms the N.sup.+ S/D electrode.