The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 1997

Filed:

Apr. 20, 1994
Applicant:
Inventors:

Keiichi Iwamura, Kawasaki, JP;

Takayuki Aizawa, Yokohama, JP;

Izumi Narita, Koganei, JP;

Takatoshi Suzuki, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M / ;
U.S. Cl.
CPC ...
364496 ; 371 381 ; 371 391 ;
Abstract

A multiplier calculates a product S'(x)=S(x).multidot..lambda.(x) mod X.sup.d-1 of a syndrome polynomial S(x) generated by a syndrome generator and an erasure position polynomial .lambda.(x) generated by an erasure position polynomial generator, modulo X.sup.d-1. A constant multiplier sequentially multiplies coefficients of the polynomial S'(x) and the erasure position polynomial .lambda.(x) with a power of a primitive root .alpha. of a code. The power exponents in this multiplication are determined in units of coefficients. Every time this multiplication is executed, an adder sequentially adds predetermined combinations of products. A plurality of arithmetic and logic operations according to the numbers of correctable erasures and errors are sequentially executed using the sums. A divisor and dividend are selected in accordance with the number of erasures included in the code on the basis of the plurality of arithmetic and logic operation results. A division is executed using the selected divisor and dividend. A value at a position, discriminated to be an error position, of the code is corrected based on the division result, thus performing error correction including erasure correction with a simple circuit arrangement.


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