Precision, analog cmos one-shot and phase locked loop including the same

Abstract

A precision CMOS one-shot having a delay proportional to a bias voltage. The bias voltage is generated by a phase locked loop which produces a bias voltage to control a voltage controlled oscillator (VCO) where the bas voltage is proportional to a difference between a first oscillatory signal and a reference oscillatory signal. Each CMOS one-shot includes a delay section for receiving the input signal and delaying production of the output signal. A current source supplies a current proportional to the bias voltage to said delay section, and the delay introduced by the delay section is proportional to the current. A latch sets the output signal of the delay section to a predetermined level after said delay has passed. An inverter is connected to an output terminal of the delay section and inverts the output signal from the delay section to generate the output signal of the one-shot. The precision one-shots may be used in a phase locked loop. The phase locked loop includes a phase error detection enable circuit that enables detection of the phase error when edge transitions are present in the data signal. This prevents clock signal generated by the phase locked loop from drifting during periods when the dam signal lacks transition. The phase locked loop is formed from a plurality of precision CMOS one-shots. The one-shots are designed using similar geometric layout on a common silicon substrate to reduce problems associated with CMOS process variation. The bias voltage, generated by a coarse phase locked loop, is applied to all the one-shots in the device to assure accurate timing.