The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 1997
Filed:
Mar. 27, 1996
Atsuhiko Ishibashi, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
An NMOS transistor (2) has a source electrode, a drain electrode and a gate electrode which are connected to a power source (VSS), an output terminal of a stepdown circuit (27), and a node (N2) between load elements (11, 12) respectively. The transistor size of the NMOS transistor (2) is so set that its drain current exerts no influence on fluctuation of an output voltage (VDD2) when an output voltage control operation by a differential amplification circuit (29) and the stepdown circuit (27) is functional to enable suppression of fluctuation of the output voltage (VDD2), while the output voltage (VDD2) is stepped down on the basis of the current quantity of the drain current of the NMOS transistor (2) when the output voltage control operation is unfunctional to disable suppression of fluctuation of the output voltage (VDD2). Thus, obtained is a voltage generation circuit which can reliably suppress fluctuation of the output voltage regardless of the frequency of fluctuation in source voltage.