The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 1997
Filed:
Jan. 16, 1996
Takeo Anazawa, Sendai, JP;
Hidetaka Fukazawa, Miyagi, JP;
Motorola, Inc., Schaumburg, IL (US);
Abstract
Propagation delay times of an input signal from an input terminal to respective gates are equalized and accelerated with a power MOS transistor that includes a plurality of transistor blocks. The transistor blocks are formed by sources being connected to each other by a first electric conductive layer (8.sub.2, 8.sub.4, 8.sub.6 and 10), drains being connected to each other by a second electric conductive layer (8.sub.1, 8.sub.3, 8.sub.5 and 9), and gates (6) consisting of a continuous semiconductor layer. The transistor has a third electric conductive layer (11) being connected to a gate terminal Gin and laminated on the gates. The third electric conductive layer laminated on the gates functions to equalize and accelerate propagation delay times of an input signal from an input terminal to the respective gates. By extending that conductive layer to near the center of a principal plane of the gate, the delay time of a gate input signal to the transistor block located at the center of the semiconductor chip can be reduced substantially.