The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 1997
Filed:
Jun. 21, 1996
Kwang-Soo Kim, Daejeon, KR;
Cheon-Soo Kim, Daejeon, KR;
Kyu-Ha Baek, Daejeon, KR;
Bo-Woo Kim, Daejeon, KR;
Electronics and Telecommunications Research Institute, Daejeon, KR;
Abstract
A method for fabricating a bipolar complementary metal oxide semiconductor device, includes a first step of forming a three-layered substrate of p.sup.- /n.sup.+ /n.sup.- type or n.sup.- /p.sup.+ /p.sup.- type and forming p- and n-wells to be adjacent to each other to the bottom of the top layer of the three-layered substrate; a second step of isolating the p- and n-wells from each other and defining a region for a bipolar transistor on one side to separate base/emitter regions from each other; a third step of defining a gate region to form a metal- oxide semiconductor transistor in each of the p- and n-wells and forming collector/emitter regions in the bipolar transistor region; and a fourth step of forming an n-type metal oxide semiconductor transistor, a p-type metal oxide semiconductor transistor and a bipolar transistor on the p-well, n-well and collector/emitter regions, respectively, and forming source/drain and base electrodes through diffusion by using a doped polycrystalline silicon sidewall spacer.