The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 1997

Filed:

Oct. 24, 1995
Applicant:
Inventor:

Kenichi Oyama, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; G11C / ;
U.S. Cl.
CPC ...
257316 ; 257319 ; 257320 ; 257321 ; 257322 ; 257324 ; 36518501 ; 36518502 ; 36518517 ; 365104 ; 365149 ;
Abstract

The invention provides an electrically erasable and programmable nonvolatile memory having a plurality of memory cells (M1 to M8) connected in series to each other to form a NAND type flash memory array. Each of the memory cells is constructed of a floating gate, a control gate, a source region, a drain region and a channel region. Each of the memory cells is formed in a semiconductor film (3a) formed on an insulating substrate. Further, a plurality of control transistors (T1 to T8) for transmitting a voltage applied to one end of NAND array to a selected memory cell in the selective writing mode are formed of a side wall of the semiconductor film. Each of the control transistors is connected in parallel to an associated one of the memory cells.


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