The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 1997
Filed:
Jun. 25, 1996
Juergen Foerstner, Mesa, AZ (US);
Myriam Combes, Plaisance-du-Touch, FR;
Arlette Marty-Blavier, Frouzins, FR;
Guy Hautekiet, Plaisance-du-Touch, FR;
Motorola, Inc., Schaumburg, IL (US);
Abstract
A method of manufacturing both bipolar and CMOS devices including vertical PNP, NPN, PMOS and NMOS devices on the same chip, includes the steps of, simultaneously forming an N+ region (14) on part of a P base region (11) of the vertical NPN device to form the emitter contact region thereof, an N+ region (14) on a part of an N- epitaxial layer (5) of the vertical NPN device to form the collector contact region thereof, N+ regions (14) on first and second parts of a P well region (8) of the NMOS device to form the source and drain thereof, and an N+ region (14) on an N base region (9) of the vertical PNP device to form the base contact thereof. In a further simultaneous step, there are formed P+ regions (15) on the P-well (8) and N base (9) regions of the vertical PNP device to form the collector and emitter contact regions thereof, P+ regions (15) on first and second parts of the N- epitaxial layer (5) of the PMOS device to form the source and drain thereof, and a P+ region (15) on part of the P base region (11) of the vertical NPN device to form the base contact region thereof.